There are many applications especially in electronic communications where it is necessary to receive and amplify signals in a relatively noisy electrical environment and where the common electrical potential of the incoming signal can vary widely. Such receivers--which are commonly referred to as line receivers--should therefore be relatively immune to electrical noise while having a high sensitivity with respect to the desired signals for reception. These receivers should further have a high common mode rejection ratio; that is, the ability to reject amplification of electrical potentials which are common to both sides of the input terminals. It is also desirable to have built-in hysteresis so as not to change the receiver's output state unless the differential input signal exceeds a predetermined value. A relatively low frequency response in relationship to the signal's frequency is also desirable so that electrical noise can be filtered to an acceptable low value. Furthermore when many receivers and transmitters share a common bus, it is further desirable that the receivers each have a high input impedance so as not to unduly load the bus and therefore the operation of transmitters on the bus.
The present line receiver achieves these design goals by providing circuitry with high sensitivity, high common mode rejection, built-in adjustable hysteresis, low frequency response in relationship to the signal frequency and a high input impedance.
The typical design of a simple differential amplifier found in the prior art is shown in FIG. 1. As shown there, input lines 20 and 21 have an input voltage impressed across the bases of two matched transistors, wherein the transistors may be of the npn or pnp type (npn type shown). This type of amplifier is known as a balanced differential amplifier since the input signal is not referenced to ground and therefore each transistor "sees" the input signal. It is readily apparent that with such an amplifier a differential signal causes an increase in the forward bias of one transistor's base (such as that for npn transistor 23) and a matched decrease in the forward bias of the other transistor's base (base of transistor 24). If the two transistors are matched and are operating in their linear mode (that is, they are neither saturated nor cutoff), the increase in the emitter current of one transistor will equal the decrease in the emitter current for the other transistor and thus the total current through resistor R.sub.E remains constant.
Correspondingly, the collector currents for the two transistors will vary in a similar manner causing a potential difference across output lines 26 and 27 due to the voltage drops across resistors R.sub.C1 and R.sub.C2. These output signals can then be further amplified with a differential amplifier circuit similar to that shown in FIG. 1 but using transistors of the opposite type (in this case of the pnp type). Alternatively, operational amplifiers of the npn type can be used if output lines 26 and 27 are buffered with emitter followers.
The common mode rejection ratio or CMRR is defined as the voltage gain for differential signals divided by the voltage gain for common mode signals. For the circuit shown in FIG. 1, assuming that the external resistor R.sub.E is much greater than the internal emitter resistance R.sub.e of transistors 23 and 24, CMRR is defined by:
CMRR=2R.sub.E /(R.sub.e1 +R.sub.e2), where R.sub.e1 and R.sub.e2 are respectively the internal emitter resistances for transistors 23 and 24.
References discussing such simple differential amplifier circuit characteristics can be found in Electronic Engineering Second Edition, Alley and Atwood, John Wiley and Sons, Inc. Publishers, 1966, pages 368-371 and General Electric Transistor Manual of 1964, pages 111-120.
In addition to such known differential amplifier circuits, Table 1 lists prior art patents which are relevant to the present invention.
TABLE 1 ______________________________________ Patent No. Inventor Patent Issued ______________________________________ 4,375,037 Ikushima 1983 4,378,529 Dobkin 1983 4,361,816 Schade, Jr. 1982 4,361,815 Schade, Jr. 1982 4,320,521 Balakrishnan et al 1982 4,317,082 Gross 1982 4,306,198 Okada 1981 4,303,891 Achstaetter 1981 4,302,726 Shobbrook 1981 4,300,102 Inoue 1981 4,297,646 LoCascio et al 1981 4,296,383 Jeandot et al 1981 4,272,728 Wittlinger 1981 4,271,394 Leidich 1981 4,271,364 Leonard 1981 4,270,092 Christopherson 1981 4,250,461 Limberg 1981 Re. 30,587 .sup. Schade, Jr. 1981 4,232,271 Dobkin et al 1980 4,216,435 Ahmed 1980 4,157,512 Schmoock 1979 4,141,033 de Boer 1979 4,137,506 Iwamatsu et al 1979 4,117,416 Schade, Jr. 1978 4,101,734 Dao 1978 4,074,205 Robe 1978 4,069,461 Sano 1978 4,063,185 Kojima et al 1977 4,055,775 Fiedler 1977 4,034,306 Barber et al 1977 4,030,043 Hamilton 1977 3,973,215 Ahmed 1976 3,958,135 Rosenthal 1976 3,936,725 Schneider 1976 3,931,580 Hebda 1976 3,921,091 Van Kessel et al 1975 3,917,991 Ota et al 1975 3,916,333 Zuk 1975 3,898,564 Waldhauer et al 1975 3,882,326 Kruggel 1975 3,769,605 Long 1973 3,739,293 Saari 1973 3,733,559 Thorpe 1973 3,638,132 Trilling 1972 3,614,645 Wheatley, Jr. 1971 3,538,449 Solomon 1970 ______________________________________
U.S. Pat. No. 4,376,529, Dobkin, discloses a differential amplifier having an input stage capable of operating in excess of the power supply voltage. It is possible for this circuit to operate from a single power supply and to function with common mode potentials outside the span of the power supply potential. The circuit employs an input stage with a pair of common base connected transistors so that the emitters comprise the circuit input terminals. The transistor collectors are coupled to a current mirror that acts as a collector bias current control and provides the signal output from the stage. The circuit must be configured to the situation where the input common range can be above the positive terminal of a single power supply in which case the input transistors are of the pnp type or where the input common mode can be more negative than the negative supply terminal, in which case npn type transistors are used. Thus, although a current mirror is employed in the circuitry, this circuitry does not disclose or suggest the use of current sourcing and sinking mirrors in combination with input resistors such that the common mode potential can both exceed the supply voltage (V.sub.cc) or be less than the supply negative potential; i.e., ground. This circuit also does not disclose or suggest the use of hysteresis circuitry for positively identifying non-common mode input signals nor the high input impedance achieved with the present invention. It is therefore submitted that this reference neither discloses nor suggests the present invention.
U.S. Pat. No. Re. 30,587, Schade, Jr., discloses a differential amplifier circuit with common emitter electrode connections to a low voltage power supply terminal and at their collector electrodes through respective current sinks to a point of reference potential. This reference discloses current sinks and current sources in an overall integrated circuit differential amplifier, including operational transconductance amplifiers (OTA's). It is particularly directed to such amplifiers where the power supply voltage magnitudes are very low such as equal to approximately twice the forward-bias base emitter voltage (V.sub.be) of a bipolar transistor. Prior art amplifiers operating at such low voltages have the problem of not being able to readily track input signals with amplitudes either greater than the power supply positive voltage or less than the power supply negative voltage if relatively high operational speed is to be maintained. In the circuitry disclosed in Schade. Jr., linear operation of the amplifier can extend to below the negative voltage of the power supply. Although the circuitry is stated as being operational for supply voltages much in excess of two times V.sub.be, including voltages up to 36 volts, no disclosure is presented stating that the amplifier is operational for common mode signals in excess of or less than V.sub.cc and ground. Indeed this circuitry does not address the problems solved by the present invention; such as obtaining a high common mode rejection ratio over an extended voltage range outside of the voltage range of the power supply, adjustable hysteresis, and high input impedance. Therefore although current sources and current sinks are used in the circuitry of Schade, Jr., it does not disclose or suggest the inventive aspects of the present invention.
The remaining references are of lesser relevance. All the cited references will be included in the file history of this patent.